I am a result-oriented and zealous youngster driven by self-motivation.
I am currently seeking an internship/co-op position in an analog/digital circuit design/testing company that tests my skills and helps me to evolve as a budding circuit designer.
I have a strong hankering for an intense engineering expertise.
I have used CAD tools to design, layout and simulate VLSI circuits. I have designed and analyzed CMOS gates, Latches, Flip-flops, basic data paths and memory building blocks.
I have analyzed LF and HF characteristics of single-stage amplifiers, two-stage amplifiers, current sources/sinks/mirrors/references. I have designed and characterized amplifiers as per design specifications in cadence CAD software.
I have knowledge in using HDL to model, analyze, optimize and design various circuits/systems.
I have used multi-output and multi-level optimizations in digital circuit designs and have knowledge in VLSI - stuck-at fault model, fault simulation and testing methodologies.
M.S. in Electrical Engineering • 2016 - Present
B.E. in Electronics and Instrumentation Engineering • 2012 - 2016
Engineering Trainee • Dec 2014 - Dec 2014
In this training, I had the opportunity to work with many people with great industrial knowledge. Here, I learned about the Operation and maintenance of Baggage Handling System, Power Supply system, Sub-stations and Air-conditioning plants in an airport.
Product Development Trainee • Jun 2014 - Dec 2014
I learned about, Introduction to Product design, Hardware design – 8051, Software design, Assembly language and Embedded C language, Keil µvision, AVR and PIC.
Trainee • Dec 2013 - Jan 2014
It was a diverse experience as I was involved in a mixed work environment. This experience gave me insights on Interface Devices, IC's (CMOS, BIOS, Power, Processor), Image Processing and Communication Protocols.
• Oct 2016 - Dec 2016
In this project, a two-stage differential input and single-ended output amplifier was designed. The amplifier was powered from a 3.3 volt power supply and a current reference of 10µA. TSMC CMOS 0.35-µm technologies were used with following specs:
• Oct 2016- Dec 2016
The design consists of 8 Number of 16- Bit Multiplier and 3 stages of 20-Bit Adder to perform the classification of system generated instruction (Based on the drone sensor network) and user-defined instruction set to classified unique decision output to the drone decision maker for action to be implemented based on comparison and choosing among the training vector sets.
We generated our own Standard cell library using Cadence design tools which included DFF, MUX2:1, XOR2, AOI221 and all other fundamental logic gates with an input slew rate of 70ps, load 30fF, 6 contacts in P diffusion and 3 contacts in N diffusion.
• Oct 2016 - Nov 2016
In this project, Cadence design tools are used to layout and characterize a falling edge triggered master-slave D flip-flop in IBM 130nm process. The input slew rate used is 70ps with the load of 30fF. D flip-flop is characterized using Silicon smart ACE.
• Nov 2016 - Nov 2016
In this project, SYNOPSYS was used to synthesize and simulate the design of an IEEE 754 Single-precision binary floating point divider which can be used for online fault monitoring/testing of analog circuits using digital signal processing.